ADT7518ARQZ【PDF 35/40 页】IC SENSOR TEMP QD ADC/DAC 16QSOP

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Sheet目录39

31页 32页 33页 34页 [35页]36页 37页 38页 39页

ADT7518

Rev. A | Page 35 of 40

The serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition, defined as a high to low transition on the serial

data line SDA while the serial clock line SCL remains high.

This indicates that an address/data stream will follow. All

slave peripherals connected to the serial bus respond to the

start condition and shift in the next eight bits, consisting of

a 7-bit address (MSB first) plus an R/W

bit, which deter-

mines the direction of the data transfer, i.e., whether data

will be written to or read from the slave device.

The peripheral whose address corresponds to the trans-

mitted address responds by pulling the data line low during

the low period before the ninth clock pulse, known as the

acknowledge bit. All other devices on the bus now remain

idle while the selected device waits for data to be read from

or written to it. If the R/W

bit is 0 the master will write to

the slave device. If the R/

bit is 1, the master will read

from the slave device.

2. Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the receiver of data. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, since a low to high transition

when the clock is high may be interpreted as a stop signal.

3. When all data bytes have been read or written, stop

conditions are established. In write mode, the master will

pull the data line high during the 10th clock pulse to assert

a stop condition. In read mode, the master device will pull

the data line high during the low period before the ninth

clock pulse. This is known as No Acknowledge. The master

will then take the data line low during the low period

before the 10th clock pulse, and then high during the 10th

clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

The I

C address set up by the ADD pin is not latched by the

device until after this address has been sent twice. On the eighth

SCL cycle of the second valid communication, the serial bus

address is latched in. This is the SCL cycle directly after the

device has seen its own I

C serial bus address. Any subsequent

changes on this pin will have no effect on the I

C serial bus

address.

Writing to the ADT7518

Depending on the register being written to, there are two

different writes for the ADT7518. It is not possible to do a block

write to this part, i.e., no I

C autoincrement.

Writing to the Address Pointer Register for a

Subsequent Read

To read data from a particular register, the address pointer

the correct address must be written to the address pointer

in Figure 56. The write operation consists of the serial bus

address followed by the address pointer byte. No data is written

to any of the data registers. A read operation is then performed

to read the register.

Writing Data to a Register

All registers are 8-bit registers, so only one byte of data can be

written to each register. Writing a single byte of data to one of

these read/write registers consists of the serial bus address, the

data register address written to the address pointer register,

followed by the data byte written to the selected data register.

This is illustrated in Figure 57. To write to a different register,

another start or repeated start is required. If more than one byte

of data is sent in one communication operation, the addressed

Reading Data from the ADT7518

Reading data from the ADT7518 is done in a 1-byte operation.

Reading back the contents of a register is shown in Figure 58.

The register address had previously been set up by a single-byte

write operation to the address pointer register. To read from

another register, write to the address pointer register again to set

up the relevant register address. Thus, block reads are not

possible, i.e., no I

C autoincrement.

SPI Serial Interface

The SPI serial interface of the ADT7518 consists of four wires:

, SCLK, DIN, and DOUT. The CS

line is used to select the

device when more than one device is connected to the serial

clock and data lines. The CS

line is also used to distinguish

between any two separate serial communications (see Figure 63

for a graphical explanation). The SCLK line is used to clock data

in and out of the part. The D

line is used to write to the regis-

ters, and the DOUT line is used to read data back from the

registers. The recommended pull-up resistor value is between

500 & and 820 &.

The part operates in slave mode and requires an externally

applied serial clock to the SCLK input. The serial interface is

designed to allow the part to be interfaced to systems that

provide a serial clock that is synchronized to the serial data.

There are two types of serial operations, read and write. Com-

mand words are used to distinguish read operations from write

operations. These command words are given in Table 59.

Address autoincrement is possible in SPI mode.

Table 59. SPI Command Words

Write

Read

90h (1001 0000)

91h (1001 0001)

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